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Title:
TEMPLATE ARITHMETIC PROCESSING METHOD AND ITS DEVICE
Document Type and Number:
Japanese Patent JPH05216988
Kind Code:
A
Abstract:

PURPOSE: To provide an arithmetic processing method and its device by which a small scale circuit can be realized, VLSI can be simplified, and a large template can be coped with by assigning an arithmetic operation to plural data processing circuits which is not concerned with the size of the template, and performing it in parallel.

CONSTITUTION: P pieces of data processing circuits 1 constituted of an arithmetic processing circuits 4, an input circuits 5 which perform a cyclic shift operation with data storage registers in the arithmetic processing circuits 4, and an output circuits 6 are serially arranged, and cyclically connected so that data can be transferred among the adjacent arithmetic processing circuits 4. Template data are simultaneously supplied through a T bus line 7 to the P pieces of arithmetic processing circuits 4.


Inventors:
ISOBE MITSUNOBU
Application Number:
JP1866992A
Publication Date:
August 27, 1993
Filing Date:
February 04, 1992
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G06T1/20; G06T5/20; G06T7/00; (IPC1-7): G06F15/66; G06F15/68; G06F15/70
Attorney, Agent or Firm:
Ogawa Katsuo



 
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