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Title:
TERMINAL CONTROLLING SECTION
Document Type and Number:
Japanese Patent JPS581234
Kind Code:
A
Abstract:

PURPOSE: To prevent the state of system stop, by reading a management data of a channel device side to a processing device with one reading instruction.

CONSTITUTION: When a processor 3 provides an instruction indicating a polling transmission and if no response is obtained from a channel device 9 even after the prescribed time to be elapsed, a control section 4 sets a reading instruction C of a register 5 to an interface register 10. When an interruption reception section 13 receives this instruction C, the operation of a line controlling section 14 is stopped, a processing section 15 is started, and line data D in a region 17 of a memory 16 is transferred to a region 7 of a memory 6 via an interface register 11. The control section 4 checks the line management data D in the region 7, and provides an instruction F instructing the transmission of a polling signal P to a terminal device 20 detected with a failure and a forced reset signal to its input/output device 20.


Inventors:
YAMAMOTO NOBORU
HASHIMOTO SHIGERU
Application Number:
JP9927081A
Publication Date:
January 06, 1983
Filing Date:
June 26, 1981
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H04L69/40; G06F13/00; G06F13/12; G06F17/40; (IPC1-7): G06F3/00; G06F3/04; H04L13/00
Domestic Patent References:
JPS5393739A1978-08-17
Attorney, Agent or Firm:
Koshiro Matsuoka