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Title:
I/O TERMINAL AND PACKAGE FOR ACCOMMODATING SEMICONDUCTOR ELEMENT
Document Type and Number:
Japanese Patent JP3673491
Kind Code:
B2
Abstract:

PROBLEM TO BE SOLVED: To provide an I/O terminal and a semiconductor package employing it in which the size and thickness can be reduced and transmission loss can be reduced at the time of inputting/outputting a high frequency signal of 20 GHz or above while ensuring required strength.
SOLUTION: At a part of a planar section 4 where line conductors 2 are exposed, first through conductors 6a are provided at intervals 8 each having a quarter of the wavelength of a high frequency signal or less such that a coplanar ground conductor 3 and a ground conductor 3c on the lower surface of the planar section 4 are connected and arranged in the direction substantially parallel with the line direction. At a part of the planar section 4 bonded with a standing wall part 5, second through conductors 6b are provided at the intervals 8 each having a quarter of the wavelength of a high frequency signal or less such that the ground conductor 3c on the upper surface of the standing wall 5 and the ground conductor 3b on the lower surface of the planar section 4 are connected through the coplanar ground conductor 3 and arranged in the direction substantially parallel with the line direction. The interval 8a between the second through conductor 6b and the adjacent side face of the standing wall part 5 substantially perpendicular to the line direction is not larger than one eighth of the wavelength of a high frequency signal.


Inventors:
Yanagisawa Mitsuo
Hisayoshi Wada
Application Number:
JP2001296629A
Publication Date:
July 20, 2005
Filing Date:
September 27, 2001
Export Citation:
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Assignee:
Kyocera Corporation
International Classes:
H01L23/38; H01L23/02; H01L31/0232; H01S5/022; (IPC1-7): H01L23/02; H01L31/0232; H01S5/022
Domestic Patent References:
JP2001185637A
JP2001144509A
JP5015508U
JP5175356A