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Title:
TEST APPARATUS
Document Type and Number:
Japanese Patent JP3364390
Kind Code:
B2
Abstract:

PROBLEM TO BE SOLVED: To take hold of the conditions of wafers in real time by checking the conditions of wafers under test in a loader with indication processing of the conditions thereof as well as checking the conditions of wafers under test on a table with indication processing of the conditions thereof.
SOLUTION: A condition indication processor 22 is provided for indicating the conditions of semiconductor wafers on an indicator 16, including their location and test progress. The processor 22 checks the conditions of the wafers in a loader which are processed for indication by a loader condition indicating processor 24 and conditions of semiconductor waveforms on a main chuck 18 i.e., a measuring stage which are processed for indication by a stage condition indicating processor 25. A graphic indication processor 26 graphically processes the wafer status on the basis of output signals of these processors 24, 25. Thus, it is possible to take hold of the wafer status in real time.


Inventors:
Hideaki Tanaka
Yuichi Abe
Application Number:
JP26514996A
Publication Date:
January 08, 2003
Filing Date:
September 14, 1996
Export Citation:
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Assignee:
東京エレクトロン株式会社
International Classes:
G01R31/00; G01R31/28; G01R31/319; H01L21/66; (IPC1-7): H01L21/66; G01R31/00; G01R31/28
Domestic Patent References:
JP831902A
JP8285910A
JP6435928A
JP425145A
JP8220107A
Attorney, Agent or Firm:
Hajime Obara