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Patent Searching and Data


Title:
TEST ARCHITECTURE FOR IDENTIFYING EVENT
Document Type and Number:
Japanese Patent JPH04297880
Kind Code:
A
Abstract:

PURPOSE: To identify an architecture with an event to be tested substantially by providing a test circuit, a comparison circuit having an internal memory for comparing an input data with a stored data and generating a matching signal in response to the comparison, and a. circuit for controlling the test circuit in response to the matching signal.

CONSTITUTION: An event identification cell 24a, b having an internal memory for detecting an identification event produces a signal indicative of the moment of time of matching which is then interpreted by an event identification module 22. The module 22 may comprises test cell registers 14, 16 and a test memory 28 and provides a timing required for rising a test logic in the circuit during normal system operation and several protocols which can be built in the circuit in order to bring about a control.


Inventors:
RII DEII UETSUTSUERU JIYUNIA
Application Number:
JP19547491A
Publication Date:
October 21, 1992
Filing Date:
August 05, 1991
Export Citation:
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Assignee:
TEXAS INSTRUMENTS INC
International Classes:
G01R31/26; G01R31/28; G01R31/3185; G06F11/22; (IPC1-7): G01R31/26; G01R31/28; G06F11/22
Attorney, Agent or Firm:
Minoru Nakamura (7 outside)