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Patent Searching and Data


Title:
TEST CIRCUIT FOR ANALOG-DIGITAL CONVERTER
Document Type and Number:
Japanese Patent JPS6042938
Kind Code:
A
Abstract:

PURPOSE: To release temporary stop of a microprocessor (MP) when an A/D converter to be tested is defective by adding a timer circuit.

CONSTITUTION: When the A/D converter A is defective and a conversion end signal AEO is not active and an AND output LO of (dotted line part of waveform 2) 1 and 2 is inputted to a hold input H1 of a microprocessor D, the processor D keeps the hold state. A timer circuit B is operated simultaneously with an output STO of a conversion start signal generating circiut S is active. The time setting is made longer to a time when the conversion end output AEO is made active. Even if the conversion end signal is not active, an output TO of the timer B is made active, and the conversion end signal and a timer output signal are inputted to an AND circuit C, the AND output LO goes to a waveform 5 as a resust, and even if the converter A is defective and no conversion end signal is outputted, the hold state of the processor D is released.


Inventors:
TSUJIMURA HIDEYUKI
Application Number:
JP15130383A
Publication Date:
March 07, 1985
Filing Date:
August 19, 1983
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
G01R31/00; H03M1/10; (IPC1-7): G01R31/00
Attorney, Agent or Firm:
Uchihara Shin