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Title:
TEST CIRCUIT FOR D/A CONVERTER
Document Type and Number:
Japanese Patent JPH05335950
Kind Code:
A
Abstract:

PURPOSE: To reduce the test time by taking notice of test of monotonous performance especially.

CONSTITUTION: A digital output of an A/D converter 2 whose monotonous performance is warranted converting an analog signal output of a D/A converter 1 into a digital signal is latched by a latch 3, all bits latched at the latch 3 in one preceding clock are inverted by an XOR gate 4 and an output of the XOR gate 4 is incremented by one at an increment circuit 5. The result is stored in a latch 6 and the incremented result and the value stored in the latch 3 in a succeeding clock are added by an adder. Thus, the monotonous performance is warranted, notice of only a most significant bit of the adder 7 is enough for the purpose and the test time is reduced.


Inventors:
SAKAI EIJI
Application Number:
JP13724992A
Publication Date:
December 17, 1993
Filing Date:
May 28, 1992
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03M1/10; (IPC1-7): H03M1/10
Attorney, Agent or Firm:
Sugano Naka



 
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