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Title:
TEST CIRCUIT OF SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP2000180517
Kind Code:
A
Abstract:

To accurately increase a test control signal without enlarging the size of a circuit by arranging a plurality of buffer cells with a different input threshold voltage where output is changed from a high level to a low one corresponding to an input voltage from a test input terminal and by generating a plurality of test control signals according to the input voltage.

A signal being inputted from an input terminal for test of a semiconductor integrated circuit is inputted into buffer cells 21, 22, 23, and 24 via a pad 20 inside the integrated circuit. In this case, in the buffer cells 21, 22, 23, and 24, an input threshold voltage (input VTH) where high and low levels are changed according to voltage being inputted into the input terminal is set to a different voltage value, thus making different the state of the high and low levels being outputted from the four kinds of the buffer cells according to the input voltage of the input terminal. The output becomes control signals a-e for test via decode circuits 27, 28, 29, 30, and 31 of the next stage, and only one of them is selected.


Inventors:
OMOTANI HISAKATSU
Application Number:
JP37594198A
Publication Date:
June 30, 2000
Filing Date:
December 18, 1998
Export Citation:
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Assignee:
RICOH KK
International Classes:
G01R31/3185; G01R31/28; (IPC1-7): G01R31/3185; G01R31/28



 
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