PURPOSE: To hold the threshold value voltage of a MOS transistor to a fixed value by holding the source potential of the MOS transistor and the potential of a P type semiconductor substrate constituting a test circuit to the same potential.

CONSTITUTION: The voltage of a Vcc/2 level generated by a Vcc/2 generator 5 is inputted to the gate of an NMOS transister(Tr) 3 when power source voltage Vcc is applied to the gate of a PMOS Tr 2. Thus, the potential of a contact point S1 is boosted according to the rise of a potential level inputted from a terminal 51 connected to the gate of the PMOS Tr1. Then, an inverter 4 is actuated when the potential level becomes a state exceeding the threshold voltage of the inverter 4, and a desired test mode control signal 101 is outputted. At this time, a source 24 is connected with a well 22 in the Tr1 formed in an N type semiconductor well 22. Thus, the source 24 and the P type substrate 21 becomes the same potential, and the threshold value voltage of the Tr1 becomes a fixed value.