To exclude factors causing an unneeded delay in logic verification of a logic circuit.
A test circuit includes: a data line that outputs input data input from an external terminal to the logic circuit and a comparison circuit, and outputs expectation value data equivalent to results of a prescribed operation to the input data input from the external terminal to the logic circuit and the comparison circuit after outputting the input data; the logic circuit that executes the operation using the input data when the input data are output from the data line, and outputs the operation result data, namely results of the operation, to the comparison circuit; and the comparison circuit that compares the expectation value data with the operation result data output from the logic circuit when the expectation value data are output from the data line and outputs the comparison result data, namely the compared results.
COPYRIGHT: (C)2011,JPO&INPIT
| JP2001176300A |
Ishibashi Masayuki
Masaaki Ogata