To prevent a reduction in the measuring number of semiconductor devices measured at the same time by outputting test pass information to a writing control part on the basis of divided test information when cycle time of a test is faster than cycle time of a failure analysis memory FAM.

When cycle time of a test is faster than cycle time of an FAM 4, a CPU 2 sets which cycle is selected as pass information of a test, and sends it to a test pass control part 6 as divided test information. When the test is started, input data for a test is sent to a DUT 7 from an ALPG 4, and fail information is sent to FAM14-1 FAM14-n through a fail information control part 12. At this time, a control part 8 converts address information from the ALPG 4 into writing information and memory selecting information to show which FAM14-1 to FAM14-n are selected, and sends it to the selected FAM, and writes fail information in its memory cell according to test pass information.