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Title:
TEST METHOD FOR READ ONLY MEMORY ELEMENT
Document Type and Number:
Japanese Patent JPS58128098
Kind Code:
A
Abstract:

PURPOSE: To releive ROMs to be tested including some failures to use them, by comparing a count integrated value with a preset discrimination level to discriminate the ROMs to be tested.

CONSTITUTION: A control circuit controls each circuit in accordance with an incorporated program, executes test for the ROMs to be tested and discriminates the result. The control circuit 10 makes an address circuit 11 to access and to read out sequentially each bit of the ROM13 to be tested and a data pattern 12 from the 0 row toward the row in parallel with 16-bit of 0WF columns, for example, to transmit the output to a comparison discriminating circuit. The address sequence and means for the readout is allowed to carry out, for certain reasons, toward the column direction in the row unit, serial scanning at each bit or at random if the method is common to both the pattern 12 and the ROM 13. A comparison circuit 14 receiving both the readout outputs of the pattern 12 and the ROM13 collates both the outputs to obtain the coincidence.


Inventors:
KOBAYASHI KAZUYA
KISHI TOSHIYUKI
MIYASAKA KIYOSHI
Application Number:
JP840382A
Publication Date:
July 30, 1983
Filing Date:
January 22, 1982
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G11C17/00; G11C11/411; G11C29/00; G11C29/08; G11C29/56; (IPC1-7): G11C17/00; G11C29/00
Attorney, Agent or Firm:
Koshiro Matsuoka



 
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