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Patent Searching and Data


Title:
TEST METHOD FOR SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2002156424
Kind Code:
A
Abstract:

To obtain an optimum rate in a test rate for shortening a test time independently of a test environment in a test method for a semiconductor device.

In advance of a normal function test of the original test method for the semiconductor device, a SHMOO of each function test is done as a pretest and a degree of allowance of the test rate is calculated from the SHMOO results. The test rate is corrected and shortened corresponding to this calculated degree of the allowance, and thereafter the function test for the semiconductor device is done using the test rate normally corrected. Therefore the test rate is properly shortened and whole test time for the semiconductor can be shortened.


Inventors:
SHINDO NAOKI
Application Number:
JP2000352900A
Publication Date:
May 31, 2002
Filing Date:
November 20, 2000
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G01R31/317; G01R31/3183; G01R31/319; G01R31/3193; G01R31/30; (IPC1-7): G01R31/3183; G01R31/317; G01R31/30
Attorney, Agent or Firm:
Hiroshi Maeda (7 outside)