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Patent Searching and Data


Title:
TEST METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH0721054
Kind Code:
A
Abstract:

PURPOSE: To improve design efficiency without requiring the remaking of a test pattern by switching an address area through which data can be inputted from the outside to a CPU to a specific address area in an ASIC loaded on the CPU.

CONSTITUTION: The test of the CPU 1 is performed by disabling a peripheral circuit test mode signal 32 from a test signal generation circuit 4 and permitting the use of both an internal bus and an external bus by the CPU 1. Furthermore, it is performed by activating a CPU signal 34 from the test signal generation circuit 4, and always selecting an output signal 35 from a CPU test area decoder 22 by a decoder selector 23. The decoder 22 sets all the residual address areas except the address area of a partial peripheral circuit on which no test is enabled as the address area for the data inputted from the outside unless it is operated with the CPU 1 when the CPU is tested. In this way, the conventional test pattern of the CPU 1 can be used, and no new test pattern is required.


Inventors:
SHIRAKI HIROYUKI
Application Number:
JP16528493A
Publication Date:
January 24, 1995
Filing Date:
July 05, 1993
Export Citation:
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Assignee:
FUJITSU LTD
FUJITSU DEVICES INC
International Classes:
G06F11/22; H01L21/66; (IPC1-7): G06F11/22; H01L21/66
Attorney, Agent or Firm:
Seiichi Samukawa