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Title:
TEST METHOD
Document Type and Number:
Japanese Patent JPS5587059
Kind Code:
A
Abstract:

PURPOSE: To obtain the measuring value closer to true value with high accuracy, by obtaining the error related to the tester as to an arbitrary sample among tested circuit (e.g. IC) and subtracting it from the tester measuring value of tested circuit of the same kind.

CONSTITUTION: Taking up an arbitrary tested circuit. e.g., IC11, the propagation delay time tpd0 between the input and output pins corresponded is manually measured with an oscilloscope, and the value is stored in the register 2 of the tester 1. Next, the IC11 is measured with the tester 1, the switch 4 is selected to the position a, the measured value tpd1 is fed to the difference circuit 5, tpd1-tpd0=Δ is obtained and it is stored in the register 3. After the preparation like this, IC11 of the same types is mounted on the measuring tool 10 of the tester 1, the propagation time tpd is measured, the switch 4 is selected to the position b, the value tpd2 is fed to the difference circuit 6, and the difference tpd2-Δ between the content Δ of the register 3 and it is obtained as the value closer to the true value.


Inventors:
KISHI KENICHI
Application Number:
JP16364778A
Publication Date:
July 01, 1980
Filing Date:
December 23, 1978
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G01R31/00; G01R31/26; (IPC1-7): G01R31/00; G01R31/26
Domestic Patent References:
JPS4878984A1973-10-23