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Title:
TEST PATTERN CREATION METHOD, SIMULATION METHOD, INFORMATION PROCESSING APPARATUS AND SIMULATION APPARATUS
Document Type and Number:
Japanese Patent JP2010244300
Kind Code:
A
Abstract:

To provide a test pattern creation method that creates a test pattern causing a race condition by a simple mechanism.

In the method, an information processing apparatus includes: a path information collection part 21 for collecting path information for test pattern creation that is information about each path from two or more input points to a race point; a simulation information collection part 22 for acquiring time information indicating a processing time required for simulation about each path indicated by the path information for test pattern creation, calculating a time difference between the processing times of the paths from the time information, and acquiring timing information for such timing as delays the time of data input to the input point to the path having the shorter processing time by the time difference; and a test pattern creation part 23 for creating a test pattern associating the path information for test pattern creation and the timing information corresponding to the set of paths specified by the path information for test pattern creation.


Inventors:
NAMEMATSU SATOSHI
Application Number:
JP2009092350A
Publication Date:
October 28, 2010
Filing Date:
April 06, 2009
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G06F17/50; G01R31/3183; G06F11/22
Attorney, Agent or Firm:
Hiroaki Sakai