PURPOSE: To test a memory address register in a high-speed channel by enabling CPU control over the high-speed channel via a low-speed bus in the test mode of the high-speed channel.

CONSTITUTION: In a high-speed channel 11, a memory address register 12 wherein address information on a low-speed bus can be preset and which can count up with a count-up signal CPU2 is provided, and its contents are outputted onto a high-speed bus by an interface gate 13. In test mode, instructions (RD instruction and SS instruction) having no relation to the input and output operation of the high-speed channel 11 are executed through the low-speed bus to make the memory address register 12 count up, and the outputting of a carry signal CRY is detected by the state of an FF16 to confirm the operation.