テスト可能な電子回路

Japanese Patent JP2008528999

A

An electronic circuit contains groups of flip-flops (12a-c), coupled to data terminals (11a-c) of the circuit and to a functional circuit (10). Each group (12a-c) has a clock input for clocking the flip-flops of the group. Each group (12a-c) can be switched between a shift configuration and a functional configuration, for serially shifting in test data from the data terminals and to function in parallel to supply signals to the functional circuit (10) and/or receive signals from the functional circuit (10) respectively. A test control circuit (16) can be switched between a functional mode, a test shift mode and a test normal mode. The test control circuit (16) is coupled to the groups of flip-flops (12a-c) to switch the groups to the functional configuration in the functional mode and to the shift configuration in the test shift mode. A clock multiplexing circuit (15a-c, 18) has inputs coupled to the data terminals (11a-c) and outputs coupled to clock inputs of the groups (12a-c). The test control circuit (16) is coupled to control the clock multiplexing circuit (15a-c, 18) dependent on the mode assumed by the test control circuit (16). The clock multiplexing circuit (15a-c, 18) is arranged to substitute clock signals from respective ones of the data terminals (11a-c) temporarily at the clock inputs of respective ones of the groups (12a-c) in the test normal mode.

JP2001005842	DEVICE AND METHOD FOR SIMULATING ELECTRIC CIRCUIT
WO/1997/043813	TIMING ADJUSTMENT CIRCUIT FOR SEMICONDUCTOR TEST SYSTEM

Have Fleury
Jean-Marc Janow

JP2007552801A

July 31, 2008

January 31, 2006

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NXP B.V.

G01R31/28; H01L21/822; H01L27/04

Kenji Sugimura
Kosaku Sugimura
Kiyoshi Kuruma
Shiro Fujitani
Tatsuya Sawada
Eiji Fujiwara

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