Title:
TESTER FOR INTEGRATED CIRCUIT FUNCTION
Document Type and Number:
Japanese Patent JPS5261938
Kind Code:
A
Abstract:
PURPOSE: The delay time of the integrated circuit to be measured is measured, and an arithmetic operation is performed between the measured delay time and set value. And the timing signal is obtained according to the operation result. As a result, the timing of measured circuit is controlled, thus securing a good measurement result.
Inventors:
SHIROSAKA SUMITOSHI
Application Number:
JP13855275A
Publication Date:
May 21, 1977
Filing Date:
November 18, 1975
Export Citation:
Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
G01R31/00; G01R31/26; G01R31/3183; G01R31/28; G06F11/22; (IPC1-7): G01R31/00; G01R31/26