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Patent Searching and Data


Title:
TESTER FOR INTEGRATED CIRCUIT OR THE LIKE
Document Type and Number:
Japanese Patent JPH02291981
Kind Code:
A
Abstract:

PURPOSE: To enable measurement of duration time of a logic data of a binary signal outputted from an integrated circuit or the like at a high accuracy in a short time by receiving a binary signal to set one FF and resetting the other FF by a logic data thereof.

CONSTITUTION: An inspector 17 provides an instruction data signal to an inte grated circuit 13 through a line 15 and a sampling clock is lead out from an oscillation circuit 18 through an output terminal 9. Signals each indicating a duration time with a logic '1' and '0' thereof measured of a binary signal lead out of an output terminal 1 of the integrated circuit 13 are inputted into input terminals 20 and 21 in bits. A reset signal is lead out of an output terminal 10 of the inspector 17. With such an arrangement, the integrated circuit 13 leads a binary signal of a discontinuous pulse corresponding to an instruction data signal 15 thereof at an output terminal and duration time of th logic '1' of th binary signal is measured to be applied to input terminals 20 and 21. Thus, a test can be made to determined whether the binary signals of the inte grated circuit 13 has respective desired duration time or not, namely, whether an oscillation frequency of an oscillation circuit 14 reaches a desired value or not.


Inventors:
ISHITSUKI NORIYOSHI
Application Number:
JP11347989A
Publication Date:
December 03, 1990
Filing Date:
May 01, 1989
Export Citation:
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Assignee:
SHARP KK
International Classes:
G01R31/28; G01R31/26; (IPC1-7): G01R31/26; G01R31/28
Attorney, Agent or Firm:
Nishikyo Keiichiro (1 outside)