Title:
TESTING CIRCUIT FOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP3725932
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To perform the diagnosis of the delay of an arbitrary part in an integrated circuit securely and readily in a testing circuit of e.g. a JTAG system, which is assembled in the integrated circuit such as an LSI and used.
SOLUTION: A register 12 for boundary scanning is provided at every input/ output pin 11 of an integrated circuit 10. The register 12 is operated by a testing clock at the time of testing. The preset value in this register 12 is displayed at the inner and outer parts of the integrated circuit 10. In this testing circuit constituted in this way, a switching mechanism 13, which selectively switch any one of the above described clock and the system clock used at the time of the system operation of the integrated circuit 10 and supplies the clock, is provided.
Inventors:
Sakae Majima
Application Number:
JP8292496A
Publication Date:
December 14, 2005
Filing Date:
April 04, 1996
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F1/04; G06F11/22; G11C29/00; G11C29/02; G11C29/56; G01R31/28; H01L21/822; H01L27/04; (IPC1-7): G01R31/28; G06F11/22; H01L21/822; H01L27/04
Domestic Patent References:
| JP6300821A | ||||
| JP5011027A |
Attorney, Agent or Firm:
Yu Sanada
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