To test a semiconductor integrated circuit whose operation frequency is more than the highest operation frequency of an LSI tester without lengthening test time.

A frequency divider circuit 20 frequency-divides test clock signals 12 to one half and turns them to 1/2 frequency divided clock signals 24. Output data D3 outputted from a signal processing circuit 2 are tentatively held by a flip-flop circuit 21, computed with the next output data D3 by a logic circuit 22 and outputted as device output data 13 through a switching circuit 23. Since the two data positioned at front and back timewise are outputted as one piece of the data, the output data D3 can be read even by the LSI tester 10 operated at a half operation frequency.