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Title:
TESTING METHOD OF PRINTED BOARD
Document Type and Number:
Japanese Patent JPS58111764
Kind Code:
A
Abstract:

PURPOSE: To enable debugging with an IC kept packaged by having a test signal inputted into the IC after a hold signal is inputted into a hole terminal of the IC to make the output terminal thereof electrically inactivated with a high impedance.

CONSTITUTION: An IC 11 with a hold terminal is packaged on a printed board 10 and has a plurality of terminals 12 comprising a normal input/output terminal, a power source terminal and the like and a testing hold terminal 13. A test signal from a tester 14 and a hold signal are fetched through an IC connection probe 15. In the debugging of the board 10, the power source of the board 10 is turned off and a probe 15 is set to terminals 12 and 13 to input the hold signal into the terminal 13. Then, when the power source is closed to the board 10, all the output terminals of the IC are made inactivated electrically with a high impedance. Under such a condition, when a test signal of the tester 14 is inputted into the terminal 12, debugging can be done without causing competition between the test signal and output signals of the IC 11.


Inventors:
TAKAHASHI YASUYUKI
OOTA YOSHIHITO
Application Number:
JP21563681A
Publication Date:
July 02, 1983
Filing Date:
December 25, 1981
Export Citation:
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Assignee:
HITACHI ELECTRONICS
International Classes:
G01R31/28; H05K13/08; (IPC1-7): G01R31/28; H05K13/08
Attorney, Agent or Firm:
Masaki Yamakawa



 
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