Title:
TESTING METHOD FOR SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP3246543
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To conduct a connection test at a high speed by confirming the connection state of measured signal terminals via a function test.
SOLUTION: VDD terminals 5-1-5-n which are power terminals are connected to signal terminals 3-1-3-n in an LSI 1 which as a semiconductor device via protective diodes 4a-1-4a-n, and the voltage value is set to 0V. A constant voltage of 0.1V from a tester 2 is applied to the signal terminals 3-2-3-n other than the signal terminal 3-1 to be measured, and the voltage value of the signal terminal 3-1 is measured. The H-level in a function test is set to a first set value of 0.2-0.3V (determined by the characteristics of the protective diodes 4a-1, 4b-1), the L-level is set to a second set value of 0.05V, the expected value is set to the H-level, and the measured voltage values of the measured terminal 3-1 are compared with them to confirm the connection state. The voltage value measurement times of the measured terminal become two to three times, however the measuring time at one time is very short at several μsec, and the total test time can be sharply shortened.
Inventors:
Fumihiko Tajima
Application Number:
JP13347196A
Publication Date:
January 15, 2002
Filing Date:
May 28, 1996
Export Citation:
Assignee:
NEC
International Classes:
G01R31/02; G01R31/28; G01R31/26; (IPC1-7): G01R31/02; G01R31/26; G01R31/28
Domestic Patent References:
| JP7113850A | ||||
| JP6109810A | ||||
| JP8105927A | ||||
| JP5448176A | ||||
| JP63225176A | ||||
| JP4110987U |
Attorney, Agent or Firm:
Nobuyuki Kaneda (2 others)