THIN FILM TRANSISTOR ARRAY BOARD AND MANUFACTURING METHOD FOR THE SAME

Japanese Patent JP2004311931

A

To provide a thin film transistor array board having thin film transistors each having a broad channel width.

On the board, gate wiring, which has gate lines and a gate electrode including a first gate electrode section and a second electrode section, is formed, and a gate insulating film is formed on the gate wiring. Then a semiconductor layer, which includes a first semiconductor section and a second semiconductor section and is made of amorphous silicon, is formed on the gate insulating layer. Further, data wiring, which includes data lines, a source electrode including a first source electrode section and a second electrode section, and a drain electrode including a first drain electrode section and a second electrode drain electrode section, is formed on the semiconductor layer, on which a pixel electrode connected to the drain electrode is also formed. At this time, divided exposure is carried out in such a way that the boundary between divided exposure areas is positioned between the first/second gate electrode sections, or between the first/second semiconductor sections, or between the first/second source electrode sections, or between the first/second drain electrode sections.

KIM DONG-GYO
YOUN JOO-AE
BAEK SEUNG-SOO
TAK YOUNG-MI

JP2003388094A

November 04, 2004

November 18, 2003

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SAMSUNG ELECTRONICS CO LTD

G02F1/136; G09F9/30; H01L21/336; H01L21/77; H01L21/84; G02F1/1368; H01L27/12; H01L29/786; (IPC1-7): H01L29/786; G02F1/1368; G09F9/30; H01L21/336

JPH11344725A	1999-12-14
JP2000194006A	2000-07-14
JP2001296553A	2001-10-26
JPH09171191A	1997-06-30
JP2000162647A	2000-06-16
JP2002258324A	2002-09-11
JPH09179141A	1997-07-11
JPS62247569A	1987-10-28

Yukio Ono
Tomoko Inazumi

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