Title:
THIN FILM TRANSISTOR ARRAY AND ITS INSPECTING METHOD
Document Type and Number:
Japanese Patent JP3191898
Kind Code:
B2
Abstract:
PURPOSE: To enable inspecting the disconnection and the short circuit of signal lines and a thin film transistor array without enlarging the substrate area of the thin film transistor array.
CONSTITUTION: Plural parallel signal lines 4, scanning lines 5 intersecting with signal lines 4 while being insulated electrically from signal lines 4, transistors 6 whose sources are and whose gates are connected respectively with signal lines 4 and scanning lines 5 at intersecting parts between signal lines 4 and scanning lines 5 are formed on a substrate and capacitance elements 14 are inserted and connected in between end edges of signal lines 4 and a power source line 15. After the capacitance elements 14 are charged for a constant time, the disconnection and the short circuit of signal lines 4 or the fault of the transistors 6 of a display part are inspected by measuring potential or current via signal lines 4.
Inventors:
Takehisa Kato
Fumiaki Emoto
Koji Senda
Fumiaki Emoto
Koji Senda
Application Number:
JP5734694A
Publication Date:
July 23, 2001
Filing Date:
March 28, 1994
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
G01R31/00; G01R31/28; G02F1/133; G02F1/136; G01R31/26; G02F1/1368; G09G3/36; H01L21/66; H01L29/78; H01L29/786; (IPC1-7): G02F1/136; G02F1/133; G09G3/36
Domestic Patent References:
| JP55866A | ||||
| JP5289102A | ||||
| JP62151769A | ||||
| JP5017599A | ||||
| JP5313132A |
Attorney, Agent or Firm:
Fumio Iwahashi (2 others)