Title:
THIN FILM TRANSISTOR ELEMENT ARRAY AND DRIVING METHOD THEREOF
Document Type and Number:
Japanese Patent JPH04280226
Kind Code:
A
Abstract:
PURPOSE:To shorten the delay time of a gate bus line by providing a shield electrode and an auxiliary bus line so as to cover the gate bus line. CONSTITUTION:A shield electrode 11 covering a gate bus line 2 is provided on the gate bus line 2 through an insulating film, and the gate bus line 2 is connected to the shield electrode 11 by through holes 12, 32 formed in the insulating film in the signal input side end part. In this case, the gate bus line 2 is connected to the shield electrode 11 by the through holes 12, 32 formed in the insulating film in two positions of the signal input side end part and the opposite side end part. Further, a second gate bus line 31 is provided on the gate bus line 2 through the insulating film, and the gate bus line 2 is connected to the second gate bus line 31 in plural positions through the contact holes 32 formed in the insulating film.
Inventors:
UCHIDA HIROYUKI
Application Number:
JP4311391A
Publication Date:
October 06, 1992
Filing Date:
March 08, 1991
Export Citation:
Assignee:
NEC CORP
International Classes:
G02F1/133; G02F1/1343; G02F1/136; G02F1/1368; G09F9/30; G09G3/36; H01L21/336; H01L27/12; H01L29/78; H01L29/786; (IPC1-7): G02F1/133; G02F1/1343; G02F1/136; G09F9/30; G09G3/36; H01L27/12; H01L29/784
Domestic Patent References:
| JPS595229A | 1984-01-12 | |||
| JPH02150822A | 1990-06-11 | |||
| JPS63208896A | 1988-08-30 | |||
| JPH02214817A | 1990-08-27 |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)