Title:
薄膜トランジスタとその製造方法
Document Type and Number:
Japanese Patent JP4169896
Kind Code:
B2
Abstract:
A TFT structure having sufficiently low resistance wiring is provided. The present invention prevents the characteristic defects caused by undercuts in a barrier metal layer. In the prior art, the undercuts are formed by a step for processing a source and a drain electrode composed of copper. The TFT structure of the present invention comprises a gate electrode on a glass substrate, a gate insulation film, a semiconductor active layer disposed on the gate insulation film so as to oppose the gate electrode, ohmic contact layers formed on both edge portions of the semiconductor active layer, and a source and a drain electrode connected to the semiconductor active layer via the respective ohmic contact layers. In addition, the source electrode and the drain electrode are formed of copper. Barrier metal layers are formed on the bottom surfaces of the source electrode and the drain electrode above areas at which the upper surfaces of the respective ohmic contact layers are located.
Inventors:
Cai Kisei
Jo Kei Tetsu
Jo Kei Tetsu
Application Number:
JP2000000521A
Publication Date:
October 22, 2008
Filing Date:
January 05, 2000
Export Citation:
Assignee:
LG Display Company Limited
International Classes:
H01L29/786; H01L21/336; H01L21/77; H01L21/8232; H01L21/84; H01L27/12; H01L29/423; H01L29/43; H01L29/45; H01L29/49; H01L31/20
Domestic Patent References:
| JP2083941A | ||||
| JP10253976A | ||||
| JP10209461A | ||||
| JP3152806A | ||||
| JP58190061A |
Attorney, Agent or Firm:
Sonoda Yoshitaka
Kobayashi Yoshinori
Kobayashi Yoshinori