Title:
薄膜トランジスタとその製造方法、アクティブマトリックス基板、及び電気光学装置
Document Type and Number:
Japanese Patent JP5563888
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a TFT allowing good production efficiency and suppressing generation of an optical leakage current.SOLUTION: In a TFT 101, a gate electrode 2 has a laminated structure including, a first metal light-shielding film A, an insulating film B, and a second metal light-shielding film C having a smaller formation area than that of the first metal light-shielding film A in the aforementioned order when viewed from a side where a substrate 1 is. The gate electrode 2 has such a structure that one of the first metal light-shielding film A and second metal light-shielding film C is electrically connected to a gate circuit, and that the other is insulated from the gate circuit. Further, the first metal light-shielding film A is formed in an area that includes a formation area of a semiconductor multilayer film 10. The first metal light-shielding film A and the second metal light-shielding film C are formed such that, in a channel layer 8, at least an area 13 between a source electrode 11 and a drain electrode 12 is close to one of the first metal light-shielding film A and second metal light-shielding film C, the one which is electrically connected to the gate circuit and such that both ends of the channel layer 8 are closed to the metal light-shielding film which is insulated from the gate circuit.
Inventors:
Koji Oda
Inoue Japanese style
Naoki Nakagawa
Inoue Japanese style
Naoki Nakagawa
Application Number:
JP2010110116A
Publication Date:
July 30, 2014
Filing Date:
May 12, 2010
Export Citation:
Assignee:
Mitsubishi Electric Corporation
International Classes:
H01L29/786; G02F1/1368; H01L21/336; H01L51/50; H05B33/10; H05B44/00
Domestic Patent References:
| JP3059542A | ||||
| JP2009237573A | ||||
| JP6347823A | ||||
| JP2010278320A |
Attorney, Agent or Firm:
Ken Ieiri
Yasuhiro Iwase
Yuichiro Sudo
Yasuhiro Iwase
Yuichiro Sudo