Title:
Three-dimensional semiconductor device
Document Type and Number:
Japanese Patent JP6203573
Kind Code:
B2
Abstract:
Provided are methods of forming a stack of electrodes and three-dimensional semiconductor devices fabricated thereby. The device may include electrodes sequentially stacked on a substrate to constitute an electrode structure. each of the electrodes may include a connection portion protruding horizontally and outward from a sidewall of one of the electrodes located thereon and an aligned portion having a sidewall coplanar with that of one of the electrodes located thereon or thereunder. Here, at least two of the electrodes provided vertically adjacent to each other may be provided in such a way that the aligned portions thereof have sidewalls that are substantially aligned to be coplanar with each other.
Inventors:
Yin Dong Tin
Lee Ning Ho
Lee Shun
Lee Tin Yuan
Application
Lee Ning Ho
Lee Shun
Lee Tin Yuan
Application
Application Number:
JP2013172535A
Publication Date:
September 27, 2017
Filing Date:
August 22, 2013
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
H01L23/522; H01L21/768; H01L27/10
Domestic Patent References:
| JP2010118659A | ||||
| JP2010192589A | ||||
| JP2011222994A | ||||
| JP2009267243A | ||||
| JP2011204829A |
Attorney, Agent or Firm:
Kyosei International Patent Office