Title:
THREE-INPUT ADDING AND SUBTRACTING CIRCUIT
Document Type and Number:
Japanese Patent JP2984606
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide the three-input adding and subtracting circuit which can obtain an arithmetic result with high precision when plural input data including both a value represented as a complement of 2 and a value represented as an absolute value are added and subtracted.
SOLUTION: Two input data are added by an adder 1 and then added by an adder 2 to 3rd input data, and the result is outputted to a selector 3. This selector 3 inputs two fixed data of OOH and FFH in addition to the output from the adder 2. A logic circuit 4 judges whether the addition result outputted from the adder 1 is a numeral represented as an absolute value or a complement of 2. Then a logic circuit 5 and a selection signal output circuit 6 outputs a selection signal for selecting one of the three data supplied to the selector 3 according to the judgement result and a carry signal from the adder 2.
Inventors:
TANIGAWA NAOMI
Application Number:
JP26213696A
Publication Date:
November 29, 1999
Filing Date:
October 02, 1996
Export Citation:
Assignee:
NIPPON DENKI AISHII MAIKON SHISUTEMU KK
International Classes:
G06F7/509; G06F7/00; G06F7/50; G06F7/76; G09G5/00; G09G5/02; G09G5/391; H04N9/67; (IPC1-7): G06F7/50; G06F7/00; G09G5/00; G09G5/02; H04N9/67
Domestic Patent References:
| JP62234490A | ||||
| JP7334346A |
Attorney, Agent or Firm:
Nobuo Takahashi (3 outside)
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