Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
THREE-LEVEL INVERTER DEVICE
Document Type and Number:
Japanese Patent JPH07213076
Kind Code:
A
Abstract:

PURPOSE: To suppress the peak value of a surge voltage and to reduce the loss, of a voltage clamp snubber circuit, which is generated in a discharge resistor by forming the snubber circuit which clamps a voltage across a capacitor to a half the voltage between the positive side and the negative side of a DC voltage source with reference to a first switching element and a fourth switching element.

CONSTITUTION: When a transistor 13 is turned off, a main circuit current as a load current is shifted to a series circuit which consists of a capacitor 24 and a diode 25. A surge voltage is absorbed by the capacitor 24, and the peak value of a voltage applied to the transistor 13 is suppressed. Then, a voltage when the transistor 13 is turned off is discharged via a resistor 26, and the voltage across the capacitor 24 is clamped to the voltage across a capacitor 11. Thereby, energy which is consumed by the resistor 26 is only the one corresponding to the voltage increment of the capacitor 24 when the transistor is turned off, a loss is reduced even when a conversion frequency is increased, a device can be made small and lightweight, and its efficiency can be increased.


Inventors:
OYAMA YUJI
MATSUURA TOSHIAKI
Application Number:
JP561894A
Publication Date:
August 11, 1995
Filing Date:
January 24, 1994
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H02M1/00; H02M7/483; H02M7/515; H02M7/5387; (IPC1-7): H02M7/5387; H02M1/00; H02M7/515
Attorney, Agent or Firm:
Soga Doteru (6 people outside)