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Title:
THREE-STATE PUSH-PULL CIRCUIT
Document Type and Number:
Japanese Patent JPS5887917
Kind Code:
A
Abstract:

PURPOSE: To make the ground level stable and to avoid the circuit operation in a semiconductor integrated circuit from being affected, by providing means decreasing the current consumption at off-state of a driving gate circuit at the prestage of push-pull output.

CONSTITUTION: In inputting 0-level to a three-state signal terminal 18, when a level of a data input terminal IN is 0, 0 is outputted from a push-pull output terminal OUT, and when a level of a data input terminal IN is 1, 1 is outputted from a push-pull output terminal OUT. In inputting 1-level to the terminal 18, since load DMOSes 14a, 14b are turned off, no current flows to NOR gates 16A, 16B substantially and when the level of the data input terminal IN is 0 or 1, the push-pull output terminal OUT is a high output impedance state. Thus, no current consumption is given to th NOR gate, the ground level is made stable, the output level is excellent and no adverse effect is given to the circuit operation.


Inventors:
MINORIKAWA KAZUO
Application Number:
JP18542281A
Publication Date:
May 25, 1983
Filing Date:
November 20, 1981
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H03K19/0175; H03K19/094; (IPC1-7): H03K19/00; H03K19/094
Attorney, Agent or Firm:
Toshiyuki Usuda



 
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