Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP3180256
Kind Code:
B2
Abstract:
PURPOSE: To use power source pads for a microcomputer also as input/output pads by providing at least one circuit of input/output circuits connected to pads connected with power source lines, and selectively connecting the circuit between the pads or the pad to the lines.
CONSTITUTION: If pads for a microcomputer are used as power source pads, a power source selection signal (1) is input to a gate of an Nch FET of a transmission gate 1, and the gate is turned ON. An output control signal (3) of an H level is input to a gate of a Pch FET of a series circuit 3 of an FET, an output control signal (3) of an L level is input to the gate of the Nch FET, and the circuit 3 is turned OFF. On the other hand, when the pads for the microcomputer are used as input/output pads, the signal (1 is set to an L level, the gate 1 is turned OFF, the signal (1) is input to an input terminal 21 through an inverter 4, an output of a NAND circuit 2 is set to a signal corresponding to a signal to be input to the other input terminal 22, and the pad is used as a function of the input pad.
Inventors:
Yukihiro Ozawa
Application Number:
JP17267992A
Publication Date:
June 25, 2001
Filing Date:
June 30, 1992
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F15/78; H01L21/82; H01L21/822; H01L27/04; (IPC1-7): H01L21/82; G06F15/78
Domestic Patent References:
| JP63141410A |
Attorney, Agent or Firm:
Seiichi Samukawa
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