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Title:
TIME DIVISION MULTIPLEX SYSTEM
Document Type and Number:
Japanese Patent JPH04109725
Kind Code:
A
Abstract:

PURPOSE: To implement a loopback test of all time division multiplexers individually by generating a timing corresponding to a location of a control path assigned on a transmission line, inserting a control signal to the location of the allocated control path and looping back a data to a controller.

CONSTITUTION: A time division multiplexer at a receiver side uses an interface section 42 to convert a transmission line interface, a drop section 34 extracts a control signal and it is sent to a communication control section 22. When the content of control represents a loopback instruction, the data is outputted to a loopback section 5 to execute the loopback test of the data. A timing generating section 6 generates a timing corresponding to the position of the control path allocated in the loopback data. A control signal insertion section 7 inserts a control signal from the communication control section 22 to the position of the control path allocated on the transmission line in matching with the timing. Thus, even when the data is looped back, the control signal is not looped back.


Inventors:
SHIROMIZU YASUBUMI
YOSHIDA HIDEKI
Application Number:
JP22877390A
Publication Date:
April 10, 1992
Filing Date:
August 29, 1990
Export Citation:
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Assignee:
NEC CORP
International Classes:
H04J3/14; H04B3/46; (IPC1-7): H04B3/46; H04J3/14
Domestic Patent References:
JPH0284832A1990-03-26
JPS60105357A1985-06-10
JPH02119335A1990-05-07
Attorney, Agent or Firm:
Naoki Kyomoto