PURPOSE: To find an obstacle place in early time by stopping the interpolation renewal of a clock information when an abnormality is detected in one clock circuit of doubled clock circuits.

CONSTITUTION: A check circuit 20 always checks the abnormality of a time information 100 output from clock circuit 10. When the abnormality is detected, said check circuit 20 communicates to a control circuit 40 that the clock circuit 10 is out of order through an error signal line 104. Similarly, a check circuit 21 checks a time information 101 of a clock circuit 11. When the abnormality is detected, said check circuit communicates to a control circuit 40 that the clock circuit 11 is out of order through an error signal line 105. The control circuit 40 performs a change-over control of a selection circuit 30 in accordance with states of error signals, 104 and 105. On the other hand, the control ciruit 40 outputs a prevention signal of a register interpolation 108 and closes a gate circuit 60, thereby stopping a new set of a time information for a register 70.