To provide a time interleave A/D conversion apparatus which makes an input signal only for clock skew adjustment and its switching circuit unnecessary, and makes an excessive analog circuit, etc. unnecessary.

The apparatus makes one of a first and a second A/D conversion circuits 11, 12 which compose the time interleave A/D conversion apparatus as a reference, and makes the other as the A/D conversion circuit of an adjusted side. An interpolator performs interpolating processing (interpolation) using output series (a plurality of sample values) of a digital filter receiving conversion output (digital signal) of the A/D conversion circuit of the reference side, obtains an interpolation value (approximation conversion result) in timing without clock skew of the adjusted side, compares the interpolation value and an A/D conversion result of the A/D conversion circuit of the adjusted side, and adjusts clock skew of the clock of the adjusted side.