PURPOSE: To obtain a time switching circuit easy for large scale integration while maintaining high-speed operation and reducing the quantity of hardware by performing address comparison in a controlling memory by a decoder circuit.

CONSTITUTION: Data A0∼A3 multiplexed in channels #0∼#3 on an input highway 1 are inputted successively to a shift register 2 for inputting. On the other hand, channel addresses of output side that exchanges and connects corresponding input data A0∼A3 are written in a controlling memory. These addresses make shifting operation on the shift register of the controlling memory 3 in parallel with shifting of corresponding input data A0∼A3 on the shift register 2 for inputting. A decoder circuits 4 are provided in correspondence to each channel of an output data memory 6, and send out a write-enable signal to a write-enable circuit 5 only when address data equal to the address of each channel are inputted from the controlling memory 3.