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Patent Searching and Data


Title:
TIMER CIRCUIT
Document Type and Number:
Japanese Patent JP11326559
Kind Code:
A
Abstract:

To provide a timer circuit for optimally obtaining stable timer time regardless of the fluctuation of a power supply voltage.

A timer circuit is provided with a ring oscillator 10 where the cycle of an oscillation signal is shortened according to the increase of power supply voltage VDD, an analog timer 40 where timer time is extended according to the increase of the power supply voltage VDD, and a ripple counter 70 that starts counting based on the output signal from the analog timer 40 and counts the number of amplitude of the oscillation signal from the ring oscillator 10 up to a specific number. Then, passage time is detected based on a value where the timer time of the analog timer 40 is added to that of the ripple counter 70, thus canceling the amount of fluctuation of the cycle of the oscillation signal from the ring oscillator 10 and the amount of fluctuation of the timer time of the analog timer 40 when the power supply voltage VDD is increased or decreased, and hence obtaining relatively constant timer time regardless of the fluctuation of the power supply voltage VDD as compared with a conventional timer circuit.


Inventors:
Takehara, Satoshi
Application Number:
JP1998000137067
Publication Date:
November 26, 1999
Filing Date:
May 19, 1998
Export Citation:
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Assignee:
ASAHI KASEI MICRO SYST CO LTD
International Classes:
G04G3/00; G04F3/00; G04G3/00; G04F3/00; (IPC1-7): G04F3/00; G04G3/00