To provide a timer circuit producing an output signal having a stabilized frequency, while reducing power consumption.

The timer circuit 10 comprises a high stability oscillator 21, a counter 22, and a frequency division value control circuit 24 where the high stability oscillator 21 generates a reference signal of a constant frequency, the counter 22 determines the frequency ratio between an internal signal and a reference signal and the frequency dividing value control circuit 24 varies the frequency dividing value of a frequency divider 12, depending on the frequency ratio. Since the difference in the frequencies between the internal signal and the reference signal can be known from the frequency ratio, frequency of the output signal can be controlled to settle at a constant value, even if the frequency of the internal signal is varied by setting the frequency division value appropriately in matching with the variation. When high stability oscillator is arranged to operate intermittently, power consumption even when a high power consumption high stability oscillator is used is reduced, and power consumption of the timer circuit as a whole can be lowered.