PURPOSE: To prevent an output from being generated at the application of electric power by using a circuit having a node provided normally to a semiconductor circuit and not going to a high level at the application of the power and connecting the node to the gate of the 3rd transistor (Tr).

CONSTITUTION: The node 39 of the circuit 30 having the node 39 provided normally to a semiconductor circuit in place of a power supply and not going to a high level at the application of the power is connected to the gate of the Tr 16 of a timer circuit 10. When the power is applied, the power supply voltage rises and a Tr 34 is conductive and the level of precharge clocks 1, 3 rises also. Thus, the level of a node 31 goes to 'H' and nodes 32, 33 being logical L go to a common level. Thus, a Tr 38 is interrupted and even when the clock 1 goes to 'H', since then node 39 does not go to 'H', the Tr 16 keeps the interrupting state. Then the level of a node 9 does not rise even after the application of the power and Tr 15 is in interrupting state as well. Then a timer output signal Tc remains logical 'L' as it is.