To provide a timing adjustment circuit that allows speedup of drawing processing of a graphic controller without changing a frequency of a clock signal of a microcomputer.

A clock signal CLK from the outside is 1/2 frequency divided by a frequency division part 12 to be given to the graphic controller 5 for generating the display data as the clock signal. When the graphic controller 5 accesses a frame memory 6, it makes a memory cycle signal MCYC active, and the timing adjustment circuit 11 detects the edges of the rise and the fall of the clock signal CLK for a period when the memory cycle signal MCYC is active, and generates a chip select signal CS when the edges are detected to give it to the frame memory 6. Since both edges of the rise and the fall of the clock signal CLK are used, the processing similar to the case that the frequency of the clock signal CLK is doubled becomes possible compared with the case using only one side edge.