Title:
フィルタ回路、送信フィルタ回路、半導体集積回路及び通信機器並びにフィルタ回路のタイミング調整方法
Document Type and Number:
Japanese Patent JP5358676
Kind Code:
B2
Abstract:
A filter circuit includes two parallel digital filters, a DAC, and an LPF. The DAC includes two parallel decoders, a parallel-to-serial converter, a switch driver, and a switch. A PLL circuit supplies a reference clock to the DAC. A frequency divider provided in the DAC divides the frequency of the reference clock by two, and supplies the half frequency clock to a parallel processing section (the two decoders and the parallel-to-serial converter) of the DAC and the two digital filters. This makes it easy to secure a timing margin, permitting use in high-speed communication on the order of several GHz.
Inventors:
Tochimaru Michiko
Heiji Ikoma
Yoshifumi Okamoto
Heiji Ikoma
Yoshifumi Okamoto
Application Number:
JP2011505676A
Publication Date:
December 04, 2013
Filing Date:
August 19, 2009
Export Citation:
Assignee:
Panasonic Corporation
International Classes:
H04B1/04; H03H17/02; H04L27/36
Domestic Patent References:
| JPH03236619A | 1991-10-22 | |||
| JPH0262124A | 1990-03-02 | |||
| JPS6460106A | 1989-03-07 | |||
| JPH0263208A | 1990-03-02 |
Attorney, Agent or Firm:
Maeda patent office
Hiroshi Maeda
Hiroshi Takeuchi
Takahisa Shimada
Yuji Takeuchi
Katsumi Imae
Kazunari Ninomiya
Tomoo Harada
Seki Kei
Yasuya Sugiura
Daisuke Kawabe
Masanori Hasegawa
Tsuguya Iwashita
Koji Fukumoto
Ryo Maeda
Mawaki Hachizo
Yukichi Matsunaga
Kenji Kawakita
Shohei Okazawa
Hiroshi Maeda
Hiroshi Takeuchi
Takahisa Shimada
Yuji Takeuchi
Katsumi Imae
Kazunari Ninomiya
Tomoo Harada
Seki Kei
Yasuya Sugiura
Daisuke Kawabe
Masanori Hasegawa
Tsuguya Iwashita
Koji Fukumoto
Ryo Maeda
Mawaki Hachizo
Yukichi Matsunaga
Kenji Kawakita
Shohei Okazawa