Title:
TIMING CONTROL CIRCUIT FOR PAM SYSTEM COMMUNICATION EQUIPMENT
Document Type and Number:
Japanese Patent JP3072509
Kind Code:
B
Abstract:
PROBLEM TO BE SOLVED: To provide timing control circuit in which no interference is caused between channels in the PAM system communication equipment using a plurality of channels.
SOLUTION: A signal ref1 from an A/D converter of a 1st channel is given to a PLL circuit 41, in which a sapling signal &phiv 1 of the 1st channel is generated, and delayed signals V1-V8 which are sequentially delayed are fed respectively to comparison and logic arithmetic sections 42B-42N and multiplexers 43B-43N. The comparison and logic arithmetic sections 42B-42N generate selective control signals V1"-V8" based on a result of arithmetic operation between signals ref2- refN from corresponding A/D converters, and the signals V1-V8 and provide an output to each corresponding multiplexer. Each of the multiplexers 43B-43N selects a signal among the signals V1-V8, base on the selective control signals V1"-V8" and provides an output of a sampling signal &phiv 2-&phiv N of the corresponding channel.
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Inventors:
Youn, Bin Yoon
Application Number:
JP1997000237248
Publication Date:
June 02, 2000
Filing Date:
September 02, 1997
Export Citation:
Assignee:
LG SEMICON CO LTD
International Classes:
B62D37/02; B62D35/00; (IPC1-7): H04L27/36; H04L7/033; H04L25/02; H04L25/40; //H03L7/06