To provide a timing error correction method capable of eliminating surely a holding error and a set-up error of an integrated circuit designed by a hierarchization design method.

In this timing error correction method for correcting timing errors by inserting timing regulation cells into the layout of the integrated circuit including a plurality of the same layout blocks in the highest hierarchy, allowances until the generation of the timing errors are arranged in the worst conditions of corresponding cells in the respective layout blocks 1a, 1b, in the cells constituting the respective layout blocks, and the timing regulation cells cd6-cd9 are inserted within the respective allowances to regulate the timing errors.