PURPOSE: To generate a clock signal having a required minimum time width for a sequence circuit by providing a monostable multivibrator connected intermittently and an FF reset by a signal from a circuit to be controlled.

CONSTITUTION: When a reset signal is made risen to a high level at starting, since a Q' output of an R-SFF13 is at a high level while the reset signal is at a low level, the monostable multivibrator 11 is triggered and a pulse having a time width T1 is outputted as a clock signal CLK. Moreover, the output triggers the monostable multivibrator 12, from which a pulse having a time width of T2 shorter than the T1 is outputted. This pulse is given to the FF13, which is set and the Q' output goes to high level and the output is given to the circuit to be controlled as an READY signal. Then the circuit to be controlled performs required operation and returns a signal ACK, causing an output of an NAND gate 15 to go to a high level, the FF13 is reset and the monostable multivibrator 11 is retriggered accordingly. The operation above is repeated and the CLK is obtained.