Title:
任意の幅を有する高解像度パルスを生成するためのタイミング発生器
Document Type and Number:
Japanese Patent JP6807945
Kind Code:
B2
Abstract:
An exemplary timing generator includes a coarse delay circuit configured to generate a coarse delayed rising edge signal and a coarse delayed falling edge signal from a reference timing signal; a fine delay circuit configured to generate a fine delayed rising edge signal from the coarse delayed rising edge signal and a fine delayed falling edge signal from the coarse delayed falling edge signal; an edge combiner configured to generate the timing signal based on the fine delayed rising edge signal and the fine delayed falling edge signal; and a masking circuit configured to generate a rising edge masking signal and a falling edge masking signal for controlling when the rising edges and the falling edges of the timing signal are generated.
Inventors:
David P. Foley
Application Number:
JP2018547389A
Publication Date:
January 06, 2021
Filing Date:
March 10, 2017
Export Citation:
Assignee:
Analog Devices Inc.
International Classes:
H03H17/08; H03K5/04; H03K5/134
Domestic Patent References:
| JP2016502799A | ||||
| JP1216617A | ||||
| JP2005522081A | ||||
| JP61039722A | ||||
| JP8274602A | ||||
| JP2011139365A | ||||
| JP2007329745A | ||||
| JP9145798A |
Foreign References:
| WO2009066765A1 |
Attorney, Agent or Firm:
Yasuhiko Murayama
Shinya Mitsuhiro
Tatsuhiko Abe
Shinya Mitsuhiro
Tatsuhiko Abe