Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
TIMING MACHINING CIRCUIT FOR DATA CLOCK
Document Type and Number:
Japanese Patent JPH03237832
Kind Code:
A
Abstract:

PURPOSE: To improve the permissible range to a pulse width distortion of an input data by applying OR calculation processing to an output data obtained through the operation of a positive logic clock and a synchronization clock and an output data obtained through the operation of a negative logic clock to the same input data and the synchronization clock.

CONSTITUTION: A data inputted from a data input terminal 1 is divided into two, the one is fed to a data sampling circuit A and the other is fed to a sub data sampling circuit A'. The sampling circuit A samples the input data by a positive logic clock. On the other hand, the sub data sampling circuit A' samples the input data by a negative logic clock, a sub synchronization pulse generating circuit C' uses a data edge detection signal from a sub data edge detection circuit B' as a reset input and generates a repetitive pulse synchronously with the output of an FF 2b. Then an adder circuit G applies the OR calculation processing to outputs of a synchronizing pulse generating circuit C and the sub synchronization pulse generating circuit C'. Thus, the permissible range of an input data with respect to the pulse width distortion is expanded without varying the basic clock.


Inventors:
Sato, Hideki
Shomura, Toshihide
Application Number:
JP1990000033507
Publication Date:
October 23, 1991
Filing Date:
February 14, 1990
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
DAI ICHI DENSHI KOGYO KK
International Classes:
G06F13/42; G06F1/12; H03K5/00; H03K5/135; H03L7/00; H04L7/033; H04L7/04; (IPC1-7): G06F1/12; G06F13/42; H03K5/00; H03L7/00; H04L7/04



 
Previous Patent: MILK FAT COMPOSITION

Next Patent: SUPPORTING METHOD OF TUNNEL