PURPOSE: To decrease the circuit scale and to make the titled circuit suitable for large scale integration by providing two counters and a logical circuit inputting the output of the said two counters to form a timing signal having an optional repetitive period without using a ROM.

CONSTITUTION: The 1st counter 11 inputs a clock signal CK and outputs an m-bit period timing pulse TP and the 1st count output signal CS1. The 2nd counter 12 repeats n numbers of operations at each timing pulse TP of m-bit period inputted from the 1st counter 11 and outputs the 2nd counter output signal CS2. The logical circuit 13 uses the signals CS1, CS2 to attain logical operation of AND/OR and outputs an object timing signal TM as the constitution.