PURPOSE: To obtain a timing signal generation circuit which makes a clock frequency high and attains high integration by varying the primary setting value of a counter by way of a logical gate with a frame pulse from outside and the ripple carry output signal of the counter.

CONSTITUTION: The output of the ripple carry terminal (RC) of a 12-bit counter 1 is inputted to the data input terminal of a D-flip-flop 6, the input terminal of an inverter 3 and one input terminal of an AND gate 4. The other input terminal of the AND gate 5 is connected with the output terminal of the inverter 3. Then, a timing signal is generated only by the output of a counter circuit. Namely, ROM for timing generation in unnecessitated, quick operation is attained, a circuit scale is reduced to a large degree and high integration is attained.